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Archimedes in an FPGA |
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MasterOfGizmo (13:33 16/4/2015)
Phlamethrower (18:13 16/4/2015)
richw (11:34 17/4/2015)
MasterOfGizmo (19:29 17/4/2015)
MasterOfGizmo (19:33 17/4/2015)
richw (20:38 17/4/2015)
sirbod (23:17 17/4/2015)
adrianl (22:21 18/4/2015)
sirbod (03:11 19/4/2015)
adrianl (09:20 19/4/2015)
MasterOfGizmo (19:41 19/4/2015)
sirbod (18:19 20/4/2015)
MasterOfGizmo (19:49 19/4/2015)
sirbod (18:48 20/4/2015)
qUE (19:28 19/4/2015)
MasterOfGizmo (19:45 19/4/2015)
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MasterOfGizmo |
Message #123550, posted by MasterOfGizmo at 13:33, 16/4/2015 |
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The main developer has done a great job the last few weeks to fix the Amber CPU core and to add all the parts missing to make it a complete Archimedes.
http://www.youtube.com/watch?v=YG_RhA6UBnk
The aim is to stay as close to the original machine as possible allowing all those old games to run.
More details here:
https://code.google.com/p/mist-board/wiki/CoreDocArchimedes
The core currently only runs on the MIST board (http://lotharek.pl/product.php?pid=96) as it makes use of the on-board controller for keyboard control and floppy emulation via SD card. In the end it may run on other FPGA boards as well.
This is no emulation but real re-implemented hardware and you e.g. need a screen capable of displaying the original screen modes.
[Edited by MasterOfGizmo at 14:35, 16/4/2015]
[Edited by MasterOfGizmo at 14:39, 16/4/2015] |
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Jeffrey Lee |
Message #123551, posted by Phlamethrower at 18:13, 16/4/2015, in reply to message #123550 |
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Excellent!
I hadn't realised that ARMv2a wasn't covered by patents and so was safe to create FPGA (or I guess pure silicon) implementations of. |
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Richard Walker |
Message #123552, posted by richw at 11:34, 17/4/2015, in reply to message #123551 |
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Also see forum thread here: http://www.atari-forum.com/viewtopic.php?t=27637
Interesting stuff. What puts me off MIST is that it seems like there is quite a small active developer community, so there is less scope for things like this to be 'finished'. Hmm... sounds familiar...  |
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MasterOfGizmo |
Message #123554, posted by MasterOfGizmo at 19:29, 17/4/2015, in reply to message #123552 |
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Yes, it's a small community. But it's growing. And of course the more potential users there are the more motivated the developers are.
This is especially true for the Archimedes as the potential user base is much smaller than for the Amiga or Atari ST.
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Archimedes in an FPGA: http://code.google.com/p/mist-board/wiki/CoreDocArchimedes |
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MasterOfGizmo |
Message #123555, posted by MasterOfGizmo at 19:33, 17/4/2015, in reply to message #123552 |
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BTW: Since the first post we got audio, a second floppy and a nice on-screen-display to select floppy disk images:
Video: Archimedes core running Xenon II and Zarch
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Archimedes in an FPGA: http://code.google.com/p/mist-board/wiki/CoreDocArchimedes |
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Richard Walker |
Message #123556, posted by richw at 20:38, 17/4/2015, in reply to message #123555 |
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Don't get me wrong, it looks amazing.
I think the potential exists for the best of both worlds: a modern piece of hardware with great Arc compatibility, yet improvements over the real thing (built in memory cards, joysticks etc.)
I will certainly keep an eye on it. |
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Jon Abbott |
Message #123557, posted by sirbod at 23:17, 17/4/2015, in reply to message #123550 |
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Looks good, although going by the slow speed of Xenon loading and the high speed of the Zarch front screen, it looks like the instruction group speeds may not match an ARM2 quite as accurately as they'd need to be.
It might be worth running !ARMSi on it and comparing the instructions against an original ARM2 - I can help with that if need be, I have a few ARM2 machines here.
What MHz ARM is it aiming to mirror? |
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Adrian Lees |
Message #123558, posted by adrianl at 22:21, 18/4/2015, in reply to message #123557 |
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Looks good, although going by the slow speed of Xenon loading and the high speed of the Zarch front screen, it looks like the instruction group speeds may not match an ARM2 quite as accurately as they'd need to be That is more likely to be the I/O than the instruction timings. The ARM2 instruction timings just drop out naturally from having a 3-stage RISC-style pipeline capable of issuing one instruction/clock. (Some months before I started writing what eventually became Aemulor, I designed an hardware implementation of the ARM2 ISA down to logic-gate level. At the time I didn't have access to FPGAs and they were much more expensive, so it has never been physically realised, but the knowledge and experience later proved useful.) |
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Jon Abbott |
Message #123559, posted by sirbod at 03:11, 19/4/2015, in reply to message #123558 |
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That is more likely to be the I/O than the instruction timings If Zarch wasn't so fast on the title screen perhaps. Something just doesn't look right speed wise.
I soak test Zarch, Xenon 2 and a few others on a daily basis so am fairly familiar with them down to code level. Xenon 2 doesn't really tax the CPU, except for the code that loads the level and graphics, the game itself ticks along at 12.5 fps.
Zarch is really heavy on RAM access but again doesn't really tax the CPU itself, so it could be RAM or bus timings.
Another game worth testing in Cannon Fodder, once it's loaded the code into memory, it does a massive decode before running the title sequence. This takes a few secs on an 800MHz CPU and a long time on an original ARM.
The simple test is as I suggested, time the instruction groups and compare - it will quickly rule out the CPU and highlight any timing issues with MUL, LDM/STM and/or RAM access timings.
[Edited by sirbod at 05:06, 19/4/2015] |
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Adrian Lees |
Message #123560, posted by adrianl at 09:20, 19/4/2015, in reply to message #123559 |
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That is more likely to be the I/O than the instruction timings
The simple test is as I suggested, time the instruction groups and compare - it will quickly rule out the CPU and highlight any timing issues with MUL, LDM/STM and/or RAM access timings.
I didn't chase the Amber link last night, but it's clear that they aren't trying to ensure that level of faithfulness in the re-implementaion; it has a 5-stage pipeline. As an aside, do you have comparison figures for those timings on your physical and emulated ARM2s? I'd be interested to see them. (I still have a couple of A3Ks, but they aren't set up; lack of space!) |
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qUE |
Message #123564, posted by qUE at 19:28, 19/4/2015, in reply to message #123550 |
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Did they reverse engineer the Archimedes or have some silicon level architecture documents which were *ahem* acquired?
Really cool project all the same |
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MasterOfGizmo |
Message #123565, posted by MasterOfGizmo at 19:41, 19/4/2015, in reply to message #123560 |
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Using the Amber core isn't so straight forward. Stephen actually had to find and fix a bunch of bugs before it would even boot into the riscos3 desktop.
Currently main focus is on getting the whole setup to run reliably and to add the very basic features to make it a pleasant gaming experience. It's not yet time to look at things like cycle exact CPU timing. Currently it can't even write to the floppy.
Regarding the pipeline: There are two incarnations of the amber core, the amber 23 with a three stage pipeline and the amber25 with a 5 stage pipeline. Stephen is using the amber23 here.
Please don't expect it to be perfect anytime soon. If you think a tiny dedicated hardware good enough for a round of Zarch on your TV might be cool, then this is for you. If you are mainly interested in a perfectly replicated CPU timing, then you probably will have more fun with a decent emulator.
The main difference with these FPGA things really is that they "feel real". It's a small box, you turn it on and it _is_ the target machine unlike an emulator which has so many aspects that permanently shout "in reality i am a windows pc" ...
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Archimedes in an FPGA: http://code.google.com/p/mist-board/wiki/CoreDocArchimedes |
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MasterOfGizmo |
Message #123566, posted by MasterOfGizmo at 19:45, 19/4/2015, in reply to message #123564 |
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Did they reverse engineer the Archimedes or have some silicon level architecture documents which were *ahem* acquired?
Really cool project all the same This is purely based on public knowledge. I e.g. did the floppy disk controller and the floppy disk timing from the data sheets of the WD1772 controller and a nec floppy drive. Both freely available on the net directly from their creators. Also emulators are e big help as you can use them to watch things happening in slow motion.
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Archimedes in an FPGA: http://code.google.com/p/mist-board/wiki/CoreDocArchimedes |
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MasterOfGizmo |
Message #123567, posted by MasterOfGizmo at 19:49, 19/4/2015, in reply to message #123557 |
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Looks good, although going by the slow speed of Xenon loading Uhm, Xenon loads from two floppy disks. How fast is this supposed to be on a real machine?
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Archimedes in an FPGA: http://code.google.com/p/mist-board/wiki/CoreDocArchimedes |
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Jon Abbott |
Message #123569, posted by sirbod at 18:19, 20/4/2015, in reply to message #123560 |
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As an aside, do you have comparison figures for those timings on your physical and emulated ARM2s? Here's my original issue 1 A310 timings and an identical machine under Arculator for comparison.
[Edited by sirbod at 19:34, 20/4/2015] |
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Jon Abbott |
Message #123570, posted by sirbod at 18:48, 20/4/2015, in reply to message #123567 |
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Uhm, Xenon loads from two floppy disks. How fast is this supposed to be on a real machine? I suppose its somewhat academic if Amber isn't aiming to be identical to an ARM2 speed wise. Very impressive what you've achieved to date though.
Should you want to compare your instruction timings against an original ARM2, see the image above which I just timed on an original A310. |
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